Steven Engel: Engineering Portfolio
Advanced Logic Design Table of Contents
Course Description
VHDL Dice Game
Final Design Project: Dashboard Future
Lessons Learned
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Undergraduate Table of Contents
Main Table of Contents
Advanced Logic Design
Spring 2022, Dr. Khorbotly
Course Description:
This course taught digital logic design at a deeper level than the previous course (Digital Logic Design), with a combination of lectures, formal laboratories with partners, and design projects which were completed individually. In this course, setup and hold violation calculations, VHDL (Very High-Speed Integrated Circuit Hardware Description Language), custom block/symbol design, and the Quartus II and ModelSim programs were taught and used to design various circuits. Additionally, a special focus was given to entrepreneurship and taking an "entrepreneurial mindset" in engineering and other areas of life.
Design Project: VHDL Electronic Dice Game Controller
One of the weekly design projects for this course was a VHDL Electronic Dice Game Controller. This was to be written entirely in VHDL; only an ASM (Algorithmic State Machine) chart and a few rules were provided to describe the function of the device:
"After the first roll of the two dice if their sum is either 7 or 11, the player wins. If the sum is 2, 3, or
12, the player loses. In all other cases the sum is referred to as a point, and the player rolls again. On the second or subsequent roll of the dice, if the sum is equal to the point, the the player wins. If
the sum is 7, the player loses. Any other sum and the player must continue to roll again until they
either win or lose."
From this information and the provided ASM chart, the truth table shown below was produced, taking advantage of plenty of don't care conditions for when the statuses of certain signals did not matter.
After this, this truth table was typed into Minilog, a program which minimizes boolean logic expressions. Minimized expressions were then determined for each of the outputs in terms of the inputs.
VHDL Code and Testing
The minimized equations were then used to write the VHDL file below, which was tested using a separate, provided VHDL testbench file. Waveforms were then produced which confirmed that the project was functioning as expected.
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The full report for this design project is given below in PDF format:
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Final Design Project: Dashboard Future
In order to practice entrepreneurship, a project was pitched by teams of two students to the class, and the grade for this project was based on how much "money" (just a hypothetical number assigned by peers) was raised, as well as the success of the projects "invested" in. For this project, an LCD text-based dashboard warning system for vehicles was proposed. It would display a brief description of what was wrong with the engine and an assigned severity level, then display the issue with the next highest severity level, eventually looping around when all issues had been displayed. The issues themselves were simulated with the switches on an Altera DE-2 FPGA board. The full laboratory report and a video of the functioning prototype are shown below:
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Lessons Learned
Some important lessons were learned in these design projects, as well as others in this course. They are listed below:
Being able to write high-quality VHDL and other hardware description languages (Verilog was learned shortly after this course was taken) is important and tremendously helpful for logic design; it allows for more complex circuits to be implemented than with schematic-based design
Understanding the concepts of propagation delay, combinational logic delay, setup time, hold time, clock skew, and setup and hold violations is critical to ensuring a system works as expected
Engineers can be tremendously successful entrepreneurs, especially if their ideas are highly feasible and well-presented
Testing circuits and extensive debugging are important parts of the design process
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